Semiconductor memory devices include, for example, a static random access memory (SRAM) and a dynamic random access memory (DRAM). A DRAM memory cell generally includes one transistor and one capacitor, thereby providing a high degree of integration. DRAM, however, requires constant refreshing, which limits use of DRAM to computer main memory. An SRAM memory cell, by contrast, is bi-stable, meaning that it can maintain its state indefinitely, so long as an adequate power is supplied. SRAM also supports high speed operation, with lower power dissipation, which is useful for computer cache memory.
One example of an SRAM memory cell is a six transistor (6T) SRAM memory cell that includes six metal-oxide-semiconductor (MOS) transistors. As processes for fabricating MOS devices migrate to nanometer technologies, the use of conventional 6T SRAM cells within processor cache memories prohibits compliance with performance requirements. To meet these performance requirements, eight transistor (8T) SRAM cells are being used in place of the 6T SRAM cells. Use of an 8T SRAM cell may enable independent sizing of the devices on the read and write ports of the memory cell for supporting a lower minimum write voltage (Vmin), while enabling a high performance read operation. Unfortunately, the use of 8T SRAM memory cells does not overcome the effect of weak bits, which are generally caused by the nanometer technology process variations on the read port devices for large size SRAM cache memory arrays.
In nanometer silicon technologies, the read/write margin for memory cells are diminished due to increased process variations. Various circuit assist techniques are commonly used to maintain scalability of the memory cell. The circuit assist techniques are also needed to improve the (Vmin) of the memory cell which is essential to enable dynamic voltage scaling on circuits incorporating the memory cells. Very low dynamic voltage scaling (DVS) is critical of low power operation of mobile CPUs using these SRAM arrays.
One of the most effective and commonly used assist techniques to improve the read/write margin is to raise the word-line (WL) voltage relative to memory cell voltage. The word-line voltage can be raised by creating a high voltage island for the memory cell. The voltage island has high design cost in terms of area, performance and power due to need of level shifter and the need of additional high voltage supply. The higher voltage supply can also be generated on-chip using charge pump circuits, however they also cost significant area and power.
Thus there is a need for efficient circuit architecture to produce voltage boost on the memory word-line that has low energy overheads and allows very low voltage operation of the SRAM array.